Generally, semiconductor devices include a plurality of circuits which form an integrated circuit fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures. Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate.
As millions and millions of devices and circuits are squeezed on a semiconductor chip, the wiring density and the number of metal levels are both increased generation after generation. In order to provide low RC for high signal speed, low k dielectric materials having a dielectric constant of less than silicon dioxide as well as copper-containing lines are becoming a necessity. The quality of thin metal wirings and studs formed by a conventional damascene process is extremely important to ensure yield and reliability. The major problem encountered in this area today is poor mechanical integrity of deep submicron metal studs embedded in low k dielectric materials, which can cause unsatisfied thermal cycling and stress migration resistance in interconnect structures. This problem becomes more severe when either new metallization approaches or porous low k dielectric materials are used.
To solve this weak mechanical strength issue while employing copper damascene and low k dielectric materials in an interconnect structure, a so called “via punch-through” technique has been adopted by the semiconductor industry. The via punch-thorough provides a via gouging feature (or anchoring area) within the interconnect structure. Such a via gouging feature is reported to achieve a reasonable contact resistance as well as an increased mechanical strength of the contact stud.
However, the argon sputtering technique (or other physical gaseous bombardment process) that is used to create via gouging features in the prior art not only removes the deposited liner material, e.g., TaN, from the trench (i.e., line opening) bottom, but also damages the low k dielectric material, specifically at the bottom of a line opening. That is a profile damaged region is created in the dielectric material at the bottom of the line opening during formation of the via gouging feature. Because of the requirement of creating the gouging feature, the final interconnect structure not only has poor liner coverage at the trench bottom, but severe damage has been introduced into the low k dielectric material from the Ar sputtering process. This becomes a major yield detractor and a reliability concern for advanced chip manufacturing.
The detailed processing steps of the existing prior art approach for via gouging are illustrated in FIGS. 1A-1E and are described herein below. Reference is first made to FIG. 1A which illustrates a prior art structure that is formed after dual damascene patterning of an upper interconnect level 108 which is located atop a lower interconnect level 100. The lower interconnect level 100 includes a first low k dielectric material 102 which includes a metallic, Cu, feature 104 therein. The lower interconnect level 100 is separated in part from the upper interconnect level 108 by a capping layer 106. The upper interconnect level 108 includes a second low k dielectric material 110 that includes both line 112 and via 114 openings located therein. A surface of the metallic feature 104 of the lower interconnect level 100 that is beneath the via opening 114 is exposed as is shown in FIG. 1A.
FIG. 1B shows the prior art structure of FIG. 1A after forming a diffusion barrier, e.g., TaN, 116 over all of the exposed surfaces. Argon sputtering, such as is shown in FIG. 1C, is then performed to clean the bottom horizontal surface within the via opening 114 and form a gouging feature (i.e., anchoring area) 118 into the metallic feature 104 of the lower interconnect level 100. The gouging feature 118 is employed to enhance the interconnect strength between the various interconnect levels shown. During the Ar sputtering process, the diffusion barrier 116 is removed from the bottom of each of the line openings 112, and dielectric damages 120 (which are indicated by circles in the second low k dielectric material 110) are formed at the bottom of each of the line openings 112. The dielectric damages 120, which can also be referred to as profile damaged regions, formed during the sputtering process are due to the inherent aggressive nature of prior art sputtering processes.
FIG. 1D shows the prior art structure of FIG. 1C after forming a metal liner layer, e.g., Ta, Ru, Ir, Rh or Pt, 122 on the exposed surfaces thereof. FIG. 1E illustrates the prior art structure after filling the line and via openings (112 and 114, respectively) with a conductive metal, e.g., Cu, 124 and planarization. As shown in FIG. 1E, the prior art structure has poor diffusion barrier 116 coverage (designated by reference numeral 126) at the bottom of the metallic filled lines and a feature-bottom roughness which is a result of the damages 120 formed into the second low k dielectric material 110. Both of these characteristics reduce the quality of the diffusion barrier 116 and degrade the overall wiring reliability. Moreover, both of the aforementioned characteristics result in the structure exhibiting a high-level of metal-to-metal leakage.
In an attempt to obviate the formation of profile damage within the line opening of an interconnect dielectric material during the formation of the via gouging feature, it is known in the prior art to replace the physical gaseous bombardment process with an isotropic etching technique. However, the isotropic profile from wet etching causes plating voids to be formed within the interconnect structure. Specifically, the plating voids are formed within the conductive material located adjacent to a via anchoring region that is created by wet etching. This prior art process is clearly illustrated in FIGS. 2A-2D. Specifically, FIG. 2A illustrates a prior art structure that is formed after dual damascene patterning of an upper interconnect level 108 which is located atop a lower interconnect level 100. The lower interconnect level 100 includes a first low k dielectric material 102 which includes a metallic, Cu, feature 104 therein. The lower interconnect level 100 is separated in part from the upper interconnect level 108 by a capping layer 106. The upper interconnect level 108 includes a second low k dielectric material 110 that includes both line 112 and via 114 openings located therein. A surface of the metallic feature 104 of the lower interconnect level 100 that is beneath the via opening 114 is exposed as is shown in FIG. 2A.
After providing the structure shown in FIG. 2A, a wet etching process is used to remove a portion of the metallic feature 104 that is exposed creating a via anchoring region 128 as illustrated in FIG. 2B. The via anchoring region 128 extends horizontally, i.e., isotropically, outward from the mouth of the via opening 114. In most cases, the horizontical etching rate along the Cu 104 and capping layer 106 interface is faster than the vertical etching rate within the Cu 104, which results in severe “undercut”, i.e., spaces between Cu 104 and capping layer 106. FIG. 2C illustrates the structure after formation of a metal liner layer, e.g., Ta, Ru, Ir, Rh or Pt, 122 on the exposed surfaces thereof. FIG. 2D illustrates the prior art structure after filling the line and via openings (112 and 114, respectively) with a conductive metal, e.g., Cu, 124 and planarization. As shown in FIG. 2D, plating voids 130 are created in the metallic feature 104 that is located directly beneath the capping layer 106 in a region abutting the via opening 114.
The presence of the plating voids is also undesirable since they decrease the reliability of the resultant interconnect structure.
In view of the above, there is a need for providing a new and improved semiconductor interconnect structure which includes a via gouging feature, yet no profile damage is created in the interconnect dielectric material underneath the conductive line, and no plating voids are created in the interconnect structure as well.